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A versatile control scheme for a parametric circuit with variable inductance
In this article, we present a control scheme for parametric circuit of the second kind, where the parameter on the inductance generated output pulses from X1 or X2. Despite the fact that the scheme uses only two logic chips, it has quite a lot of redundancy. So, if the device is not designed for switching power (the power of parametric DC circuit), then the entire chain associated with the chip DA2, can be eliminated.
The circuit can operate up to 300 kHz, the pulse output X1 relative to X2 and X3 at any phase, be divided into 1 and 2, the frequency of X2 and X3 relative to X1 and to form the output X2 of the pulses of any duty cycle. Because her work applies a relatively strong inverter circuits DD1, to control the output movetime (outputs XS1.1 and XS1.3) do not require additional drivers.
Универсальная схема управления параметрической цепью
The scheme is divided into two parts: a master and an output. Output is to the right of the connector XS1, we'll talk about it later.
Specifies the scheme works as follows. Specifies the generator on DD1.1-DD1.2 generates pulses which are fed simultaneously into two RC-chain: R3R4C2 and R3R5C3, shifting the phase of the output signal X1 relative to X2 and X3. Regulireba is a multi-turn resistor R3. Pulses from the bottom of the chain transferred to the frequency divider for DD2.1, and the input half-bridge driver for DA2 (if any). The output X2 of the length of the pulses is regulated by a resistor R8, and generates a chain R8R9C5 and DA2.2, the entrance of which is connected through another phase-shifting the chain, collected R6R7C4. She, in turn, switches SA1 through between the signal from a frequency oscillator, and a signal with a frequency that is two times less. As additional settings are applied, the switches SA2 and SA3, which allow to invert the output signals.
The output part of the circuit consists of two keys VT1 and VT2 and two keys VT3 and VT4 controlled half-bridge circuit DA2. As already mentioned, the scheme is redundant, and in some cases, VT3, and VT4 is not needed. Then from the diagram you can eliminate DA2 and all its piping, as well — no need to install a capacitor C5. I must say that the output part of this circuit may be completely different, it all depends on what impulses you need to get the output and what they demanded.
As DD1 used chip MC14502B. Instead, you can use an indirect analog of the CD4049, but the layout of the legs she had a totally different — pay attention to it! Domestic counterparts К561ЛН1 and K561LN2 is not recommended because of load capacity, they have several times less, or then put on the outputs XS1.1 and XS1.3 additional drivers.
D-trigger DD2 has a larger range to select analogues. Here you can apply as Otechestvennoy chip K561TM2and its direct counterpart — CD4013.
Voltage stabilizer DA1 12V standard LM7812, or its Soviet counterpart — КРЕН8Б. The VD1 diode — 1N4148or any similar. VD2 diode — UF4007 or UF4006.
Keys VT1-VT2 is desirable to use a series of "lightweight" — with a small input capacitance. Under such characteristics are suitable IRF740 or IRF840. Key VT3-VT4 will fit almost any MOSFET's N-channel and control voltage in 12V. In any case, the choice of output transistors you need to cut the upper limit voltage, which may appear on their drains. Driver half-bridge DA1 — IR2109; it can be replaced by a similar IR2104 or IR2108. In this case the 3rd leg of these circuits must be connected to +12V.
Capacitors C1-C5 is designed for high frequency oscillator to 3.3 kHz. For any other frequency in proportion to need to change these values. For example, we want the average driver frequency was 1 kHz, then the values of capacitances C1-C5 must be multiplied by 3.3. Resistance remain the same.
Below are pictures of the PCB for the device described above. The Board doesn't have DA2 and binding, but left a place for this chip in case you will need access X3. Guests can choose to make your own version using the layout editor DipTrace.
Печатная плата для схемы управления параметрической цепью Печатная плата с расположением деталей для схемы управления параметрической цепью Печатная плата для схемы управления параметрической цепью (сторона с деталями)

© Vyacheslav Gorchilin, 2017
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